1. Field of the Invention
This invention relates to a microprocessor, which has a bank structure, and a data processing system in which said microprocessor is incorporated. In particular, this invention relates to a microprocessor which has a structure to conduct data processing by connecting a particular memory (bank RAM), which is mapped on an address map of a data processing system, with a group of registers contained in this microprocessor, and the data processing system itself.
2. Description of Prior Art
Generally speaking, in a data processing system, such as a microprocessor system, memory devices having high-speed access ability and multi-ports are incorporated as general purpose registers in the microprocessor (referred to as MPU, below). The number of such devices which can be contained in the MPU is limited by the size of a semiconductor chip.
Consequently, a microprocessor system having a bank structure has been proposed. In this system, the word `bank` means a group of registers which are mainly used for operations in the MPU. In usual, the number of banks for one task is determined according to the MPU program. In actuality, several banks are incorporated in the MPU. When a task is switched into another, a group of registers, that is, a bank, is switched into another. As mentioned above, the number of banks incorporated in the MPU is limited according to the chip size of this MPU. Therefore, many banks cannot be incorporated in the MPU.
In order to increase the number of banks which can be utilized by the MPU, a system having an external memory is proposed. In this system, banks are saved in areas of a special memory (bank RAM) mapped on the address map of this MPU. When a particular bank saved in a certain area of the bank RAM is recalled by the MPU, the data in said area is taken out from the memory and loaded on the bank in the MPU. In this case, if the data transfer between a bank inside the MPU and the bank RAM outside the MPU is carried out through external buses, the MPU must stop for a long time until the bank exchange is completed. Therefore, the data transfer between the bank in the MPU and the bank RAM is conducted through a dedicated bus at a high speed.
As mentioned above, in the microprocessor system having the bank structure, bank exchange between the bank RAM outside the MPU and the bank in the MPU is conducted through the dedicated high speed bus, instead of external buses. In this system, however, the following problem arises. When a peripheral device of the MPU accesses the bank RAM through external buses, the device does not recognize whether the content in the accessed area of the bank RAM is now in use by the MPU as a bank or not. Only the MPU recognizes whether the content accessed by said peripheral device is now in use by itself, or not. Accordingly, when the MPU uses the bank RAM as a bank, the peripheral device is able to access only the old information of the bank RAM. In other words, when the MPU uses the bank RAM as a bank, the peripheral device cannot access the newest information in the bank RAM.